Variable length instructions refer to instructions that have variable word length. For example, in a variable length instruction set, the length of the instructions may be 1 byte, 2 bytes, 3 bytes, 4 bytes, or even more bytes. Fixed length instructions refer to instructions that have fixed word length. For example, the length of every instruction is 4 bytes in a fixed length instruction set. In general, a variable length instruction set is used in Complex Instruction Set Computer (CISC), whereas a fixed length instruction set is used in Reduced Instruction Set Computer (RISC).
Generally, every instruction in the fixed length instruction set completes an operation (or an action), thereby better utilizing efficiency of pipeline execution; whereas some instructions in the variable length instruction set often need to complete multiple operations (or actions) in steps, causing a pipeline in a pause status, thereby reducing pipeline throughput and the overall performance of a processor system.
One solution of the above problem is that a central processing unit (CPU) core (also called processor core) which executes the instructions in the fixed length instruction set is used to generate a variable length instruction address. Based on the variable length instruction address, an instruction is obtained from a memory. Before executing the variable length instruction, the variable length instruction is converted to one or more fixed length instructions. Then, the CPU core executes these fixed length instructions, thereby increasing the pipeline throughput. However, the conversion may increase the depth of the pipeline. Thus, more pipeline stages need to be cleared when branch prediction is wrong, thereby reducing the overall performance of the processor system.
In addition, a cache is generally used to duplicate a part of content from a lower level memory in current processor architectures, so that the duplicated content in the cache can be quickly accessed by a higher level memory or the CPU core and thus to ensure pipeline for continuous execution. In a basic cache structure, after a cache miss occurs, contents in the lower level storage medium is filled into the cache, such that the pipeline has to pause to wait for miss contents to be filled into the cache. Some new cache structures, such as victim cache, trace cache and prefetching, are introduced based on the above cache structure, improving the above structure. Therefore, with a widening gap between processor speed and memory speed, the current computer architectures, especially various kinds of cache misses, become still the most serious bottleneck in increasing the performance of modern processors.